1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device of an open bit line structure having a boosting voltage generating circuit.
2. Description of the Related Art
In a semiconductor memory device such as a synchronous dynamic random access memory (SDRAM), a boosting voltage which is higher than a power supply voltage, i.e., a boosting voltage which is a power supply voltage plus a threshold voltage of a cell transistor, should be applied to a gate of the cell transistor in order to transmit data stored in a cell capacitor to a bit line.
The boosting voltage is used as a power source of various circuits as well as the gate of the cell transistor. A boosting voltage generating circuit has a boosting voltage detecting circuit to compensate for insufficient charge whenever a level of the boosting voltage is lowered to thereby retain the boosting voltage at a constant level.
FIG. 1 is a schematic view illustrating a memory cell array of an open bit line structure. The memory cell array 100 includes n memory cell array blocks 10-1 to 10-n, bit line sense amplifiers S/A arranged between the memory cell array blocks 10-1 to 10-n, a plurality of memory cells C connected between word lines WL and bit lines BL, and a plurality of dummy memory cells DC connected between the word lines WL and dummy bit lines DBL. Of the memory cell array blocks 10-1 to 10-n, end memory cell array blocks 10-1 and 10-n which are located in an end region of the memory cell array include memory cells C connected between the word lines WL and the bit lines BL, and dummy memory cells DC connected between the word lines WL and the dummy bit lines DBL, and the dummy bit lines DBL are connected to a bit line voltage VBL.
However, in the memory cell array of the open bit line structure, in the case where the end memory cell array blocks 10-1 and 10-n are selected, two word lines WL1 are simultaneously activated. On the other hand, in case where one of the central memory cell array blocks 10-2 to 10-(n−1) which are located in a central region is selected, only one word line WL is activated.
Since in the end memory cell array blocks 10-1 and 10-n, half of the memory cells connected to the selected word line WL1 are the dummy memory cells, in order to satisfy the same condition as a case where the central memory cell array block is selected, twice as many word lines should be activated. Thus, if the end memory cell array blocks 10-1 and 10-n are selected, since twice as many word lines as when the central memory cell array blocks 10-2 to 10-(n−1) are selected should be activated, a larger boosting voltage is required.
FIG. 2 is a block diagram illustrating a boosting voltage generating circuit of a conventional semiconductor memory device. The boosting voltage generating circuit 200 includes: a boosting voltage VPP activating signal generator 15 which outputs a boosting voltage enable signal VPP-EN1 in response to an activation signal of a row address strobe signal RAS/; a first boosting voltage generating means 110 which operates in response to the boosting voltage enable signal VPP-EN1 to output a boosting voltage higher than a power supply voltage to an output terminal; a second boosting voltage generating means 120 which is enabled in response to the boosting voltage enable signal VPP-EN1 and receives the boosting voltage of the output terminal to detect whether the boosting voltage VPP is maintained at an appropriate target level to perform a pumping operation; and a third boosting voltage generating means 130 which is enabled when the power supply voltage VDD is applied in standby and active is modes and receives the boosting voltage of the output terminal to detect whether the boosting voltage VPP is maintained at an appropriate target level to perform a pumping operation.
The first boosting voltage generating means 110 is always activated in the active mode and includes a boosting voltage VPP driving means 25 which is synchronized with the boosting voltage enable signal VPP-EN1 to operate, a first driving signal generator 5 for outputting a first driving signal DRV1 in response to an output signal of the driving means 25, and first and second pumps 3 and 13 for supplying boosting voltage charge to an output terminal in response to the first driving signal DRV1.
The second boosting voltage generating means 120 is selectively activated in the active mode and includes an active boosting voltage VPP level detector 35 which operates in response to the boosting voltage enable signal VPP-EN1 and the level of the boosting voltage VPP of the output terminal, a second driving signal generator 55 for outputting a second driving signal DRV2 in response to an output signal of the detector 35, and third and fourth pumps 23 and 33 for supplying boosting voltage charge to an output terminal in response to the second driving signal DRV2.
The third boosting voltage generating means 130 always operates in the standby and active modes and includes a standby boosting voltage level detector 45 which operates in response to the power supply voltage and the level of the boosting voltage VPP, a third driving signal generator 65 for outputting a third driving signal in response to an output signal of the detector 45, and a fifth pump 43 for supplying boosting voltage charge which is necessary to an output terminal in response to the third driving signal DRV3.
The second boosting voltage generating means 120 detects whether or not the boosting voltage is maintained at an appropriate level in the active mode and performs a pumping operation through the third and fourth pumps 23 and 33 to supply additional charge to the output terminal to thereby maintain the level of the boosting voltage constant when it is lower than the appropriate level.
However, in the semiconductor memory device of the open bit line structure, when the end memory cell array blocks 10-1 and 10-n are selected, the boosting voltage is excessively lower than when the central memory cell array blocks 10-2 to 10-(n−1) are selected. Consequently, it is difficult to rapidly compensate for insufficient charge to maintain the boosting voltage at a constant level.